Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.
Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
Good handle on IR/EM related issues in memory layouts.
Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
Experience & or strong interest in memory compilers developed.
Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Hardware, Technical Support, Telecom Engineering
Role Category: IT Hardware
Role: Hardware Design Engineer
LVS DRC Layout Design Physical Verification Synopsys DFM Cadence Design Engineering Design Engineer Memory Layout
Desired Candidate Profile
PG – Any Postgraduate
Doctorate – Doctorate Not Required